1. Field of the Invention
The present invention generally relates to a semiconductor memory unit. More specifically, it relates to a redundant circuit technology used in the semiconductor memory unit.
2. Description of the Related Art
Despite the demand for large capacity highly integrated semiconductor memory units, it is generally difficult to manufacture memory cell arrays containing no faulty bits (i.e., detected faulty memory cells). For example, in using the latest circuit technology to mass produce memory cell arrays, the failure rate of the memory cells in the initially produced lots tends to be very high. This makes the yield rate of effective memories unacceptably low. Since there are usually only a few defective bits for each cell array, it is generally not economical to discard the entire defective array.
The technology for replacing a column and row of a defective memory cell with a spare column and row, prepositioned in the regular memory cell array, is in great demand and consequently widely studied. This technology is generally called redundant circuit technology, and the spare column and row are most often called a redundant column and row. In circumstances where the column and row are replaced in the above-described manner, normal semiconductor memory operations can be carried out, even when the address of a faulty bit coincides with an externally designated memory address provided by means well known to those skilled in the art.
FIG. 3 is a block diagram showing a fundamental circuit diagram of a conventional DRAM (Dynamic Random Access Memory) utilizing redundant columns. The DRAM is primarily constructed with a matrix memory cell array 51 having a minimum data storage unit for each cell 52 of one bit of datum. The array 51 is constructed with memory cells 52 arranged in a two dimensional manner defined by row and column directions. The cells 52 which are arranged in a row are coupled to a word line (hereinafter referred to as WL), while the cells 52 that are arranged in a column are coupled to either a bit line (hereinafter referred to as BL) or to an inverted bit line (hereinafter referred to as bar BL). A pair of bit lines BL, bar BL are arranged to mutually associate with each other and are coupled to a cross couple latch type sense amplifiers 53 (hereinafter referred to as SA). The state of the signal level in each of the paired bit lines BL and bar BL are logical complements of each other.
The memory cell array 51 is divided into two regions: a regular memory cell region 51a and a redundant memory cell region 51b. One set of the paired bit lines BL and bar BL is provided to the redundant memory cell region 51b. A single redundant column includes the cells 52 which are serially coupled to the set of bit lines BL, bar BL, respectively. Each WL is coupled to a row decoder 54. When a row address is externally designated, the row address is transferred to the row decoder 54 through a row address buffer 55 allowing the row decoder 54 to select a WL corresponding to the designated address.
Each SA 53 is coupled to an I/O and bar I/O line through an associated transfer gate 56. The data communicated via the I/O and bar I/O lines is input to a read amplifier 57 (hereinafter referred to as RA) which provides for amplification of the data signals. The RA 57 outputs the amplified signal to an output circuit 58 which outputs data through a data bus (hereinafter referred to as DB) and an inverted data bus (hereinafter referred as bar DB). Output circuit 58 in turn provides output of data to external circuitry (not shown). The logical states of the digital signals communicated by lines I/O and bar I/O, as well as, lines DB and bar DB are the logical complements of each other.
The transfer gates 56, disposed in the regular memory cell region 51a, are coupled to a column decoder 59 through column select lines (hereinafter referred to as CSL). Each of the gates 56 are constructed with a pair of NMOS transistors coupled between the SA 53 and the I/O and bar I/O lines. The gates of the transistor pairs are connected to a column decoder 59 by the CSL. Therefore, when the signal state of the CSL rises to a high level (hereinafter referred to as H level), the transfer gates 26 of the NMOS transistors switch to a conductive ON state.
The conventional redundant memory cell includes the SA 53b coupled to a set of bit lines BL and bar BL in the redundant memory cell region 51b. The redundant memory cell further includes an amplifier SA 53b coupled with a transfer gate 56b. The transfer gate 56b communicates to a redundant column driver 60 through a redundant column select line RCSL. Therefore, when the state of the RCSL rises to a H level, the pair of NMOS transistors comprising the gate 56b are actuated and cause the gate 56b to turn to an ON condition. When a column address is externally designated, the column address is transferred from a column address buffer 61 to the column decoder 59 to provide memory cell address information to address transition detector 62 (hereinafter referred to as ATD) and to spare decoder 63.
The SA amplifiers 53 and 53b amplify the data transferred through the BL and bar BL upon sensing the set of the paired bit lines BL and bar BL which are coupled as a reference to the selected memory cells 52. The ATD 62 detects that a column address has been externally designated, generates a pulse signal ATD1 containing a single pulse, and then outputs it to a column decoder 59, a spare decoder 63, and a delay circuit 64. The delay circuit 64 delays the pulse signal ATD1 by a predetermined length of time, and generates it as a pulse signal ATD2 containing a single pulse. The signal ATD2 is then output from the delay circuit 64 to the column decoder 59 and redundant column driver 60.
Nonvolatile elements such as fuse elements, etc. are disposed in the spare decoder 63 for storing the column addresses of defective memory cells. Manufacturers of DRAM's commonly inspect whether or not a DRAM contains memory cells that are defective in the regular memory cell region 51a just prior their shipment. If the inspected DRAM contains defective memory cells in the memory cell array 52, the manufacturer usually programs the column addresses of the defective cells in the spare decoder 63.
The spare decoder 63 is actuated by the pulse signal ATD1 to read out the column address and compares the stored column address of the defective cells 52 with the externally designated column address. When both column addresses coincide each other, the space decoder 63 generates a redundant signal (hereinafter referred to as RS) which is either at a H or low level (hereinafter referred as to L level). That RS signal is then output to the column decoder 59 and redundant column driver 60.
The column decoder 59 is actuated by the signals RS and ATD2, and in turn selects a column (one set of paired bit lines BL and bar BL) in the array 51 which corresponds to the externally designated column address. The decoder 59 is set to a stand-by condition when initialized with signal RS at either a H or L level, and then becomes actuated when the ATD2 is coupled thereto. The actuated column decoder 59 selects a CSL corresponding to the externally designated column address, and sets the state of CSL to a H level. Therefore, any transfer gates 56 coupled to the CSL are switched to a conductive ON state. As a result, a column corresponding to the externally designated column address in the regular memory cell region 51a is selected through the SA amplifiers 53 via the transfer gates 56.
The redundant driver 60 is likewise actuated by the signals RS and ATD2, and selects a column (one set of paired bit lines BL and bar BL) in the redundant memory cell region 51b. The driver 60 is set to a stand-by condition when initialized with signal RS at either a H or L level, and is subsequently actuated by the input of signal ATD2. The actuated driver 60 sets the state of RCSL to a H level thereby switching transfer gate 56b to an ON condition. In this way, the column in the redundant memory cell 51b is selected by means of the SA 53b and the gate 56b.
The level of the signal RS which sets the driver 60 to an active stand-by condition differs from the signal level required to activate the column decoder 59 to the active stand-by condition. That is, either the column decoder 59 or the redundant column driver 60 is switched to an active stand-by condition depending on whether RS from the spare decoder 63 is at a H or L level. Subsequently, either the decoder 59 or driver 60 is actuated in response to signal ATD2.
The read out operations from the DRAM which is constructed in accordance with the above-described arrangement will now be described.
If the defective memory cells 52 exist in the regular memory cell region 51a, the spare decoder 63 stores the column addresses of the defective cells 52. When data stored in specific addresses in the memory cell array 51 is to be read, a column and a row addresses are first externally designated and then transferred from the row address buffer 55 to the row decoder 54. AWL corresponding to the designated row address is selected by means of the row decoder 54. As the WL is selected, each of the memory cells 52 coupled to the row decoder 54 is selected. The data stored in the cells 52 is then transferred to either the BL or bar BL lines coupled to the cells 52.
When a column address is externally designated, the address is transferred from the column address buffer 61 to the column decoder 59, to ATD 62, and to spare decoder 63. The ATD 62 detects that a column address has been externally designated based on a change in the column address. It next generates a pulse signal ATD1 containing a single pulse, which is output to the spare decoder 63 and the delay circuit 64.
The spare decoder 63 is actuated by pulse signal ATD1, and compares the stored column addresses of the defective memory cells 52 with the externally designated column address. When both column addresses coincide, the spare decoder 63 generates a H level signal RS, and outputs it to the decoder 59 and the driver 60. When no defective memory cells 52 exist in the regular memory cell region 51a, or when the externally designated column address differs from the column address of the defected memory cells 52, the state of a redundant signal RS is output from the spare decoder 63 at a low level. This low level signal RS sets the driver 59 to an active stand-by condition and prevents the driver 60 from being so set.
The pulse signal ATD1 is also output to circuit 64 where it is delayed by a predetermined length of time. Delay circuit 64 next generates an output pulse signal ATD2 containing only one pulse which is output to the column decoder 59 and to the redundant column driver 60. Since the driver 60 is not in the active stand-by condition, it's condition remains unchanged even though the driver 60 receives signal ATD2. Conversely since the column decoder 59 is set to an active stand-by condition, it will be actuated when it is provided with signal ATD2.
When the decoder 59 is actuated, it first selects the CSL data line corresponding to the externally designated column address, and then sets the selected CSL to a H level. Accordingly, the transfer gate 56 coupled to the CSL is switched to a conductive ON state. In this way, a specific column within the regular memory cell array region 51a is selected by means of the corresponding SA amplifier 53 and the transfer gate 56 in order to provide an address which corresponds to the externally designated column address. That is to say, when a row (i.e., WL) and column (i.e., set of paired bit lines-BL, bar BL) of the memory cell array 51 correspond to the externally designated row and column address, a single memory cell 52 address is selected for the purpose of reading its datum. Using this circuit construction, when signal RS is at a L level, the column decoder 59 is actuated to select the memory cell 52 in the regular memory cell region 51a corresponding to the externally designated column address. The datum stored in the selected cell 52 is then read out.
The data stored in the selected memory cells 52 is transferred from the SA 53 to the I/O and bar I/O lines through the actuated transfer gate 56. The I/O and bar I/O lines input this data to the RA 57 which in turn amplifies and outputs the data signal to output circuit 58 by means of lines DB and bar DB. Output circuit 58 next outputs the amplified datum or data to an external device not shown. If the address stored in the spare decoder 63 is not the same as the externally designated column address, it can be determined that no defective memory cells exist. Under these circumstances, the data stored in the regular memory cell region 51a is accessed in a normal fashion.
Conventional DRAM technology using redundant columns as substitutes for defective memory cells will now be described when a RS signal from the spare decoder 63 is set to a H level.
When signal RS is output from the spare decoder 63 at a H level, the redundant column driver 60 is set to an active stand-by condition. Column decoder 59 is thereby prevented from being set to the active stand-by condition. The delay circuit 64 generates a signal ATD2 in a way similar to that described above, and outputs the signal to the column decoder 59 and the redundant driver 60. Since the driver 60 is set to an active stand-by condition, it will be actuated when coupled with signal ATD2. When actuated, the driver 60 sets the signal of RCSL to a H level. Accordingly, the transfer gate 56b is switched to a conductive ON state. Therefore, the column (i.e., one set of the paired bit lines BL, bar BL) in redundant memory cell 51b is selected via the SA 53b and the transfer gate 56b. This column selection, together with a row selection as described above delineates the selection of a specific redundant memory cell. Only the datum stored in the selected memory cell 52 is transferred from the SA 53b to the I/O and bar I/O lines through the activated transfer gate 56b. This datum is then communicated to external circuitry in a fashion similar to that described above. Thus, given an external designation of a defective memory cell's address, a column in the redundant memory cell region 51b may be selected for use rather than a column in the regular memory cell region 51a.
The reason for providing the delay circuit 64 is to prevent the column decoder 59 and redundant column driver 60 from being simultaneously activated. In the case where the delay circuit 64 is not provided, the column decoder 59 and the redundant driver 60 can be simultaneously activated. When the decoder 59 and the driver 60 are simultaneously actuated, the memory cells 52 in both regular memory region 51a and in the redundant memory cell region 51b are simultaneously selected and information contained therein is transferred to the I/O and bar I/O lines. However, only one bit of datum at any particular time is permitted to be communicated by the I/O and bar I/O lines. Therefore, data simultaneously transmitted through the I/O and bar I/O lines tends to be destroyed. This destruction is commonly referred to as data demolition. As a result, no desired datum is transferred to the RA 57 or subsequently through the output circuit 58 to external circuitry.
To prevent this from occurring, signal ATD1 is delayed by delay circuit 64 for a predetermined length of time, and output as ATD2 after signal RS, based on the externally designated column address, is output from the spare decoder 63. In other words, the delay circuit 64 delays the ATD2 based on the operational cycle of the spare decoder 63 (i.e., the length of time between the activation by the ATD1 and the generation of the RS based on the externally designated column address). As a result, the memory cells 52 in the regular memory cell region 51a and in the redundant memory cell region 51b are not simultaneously selected. Therefore, the data demolition in the I/O and bar I/O is prevented. Unfortunately, the delay circuit 64 increases the length of the access time required for reading out data, and retards the high speed operation for processing the data in the semiconductor device.
The present invention increases circuit performance by having as its primary object to provide a semiconductor memory unit having the simple structure which shorten the length of access time required for reading out data from a memory cell array.